The Problem: Calculators Don’t Match Reality
Every CAD tool and online calculator can estimate trace impedance from geometry. The formulas are mathematically correct. Yet fabricators routinely adjust trace widths from what designers specify - sometimes by 10-20% - to hit the target impedance after manufacturing.
Why the disconnect? Real-world impedance depends on variables that calculators can’t fully model:
- Actual etch profile - traces aren’t rectangular; they’re trapezoidal, and the taper varies by copper weight, etch chemistry, and line width
- Specific prepreg construction - Dk varies with resin content, glass style, and layer position in the stackup
- Copper foil type - RTF, VLP, HVLP each interact differently with the dielectric
- Process variations - plating thickness, lamination pressure, material lot differences
- Solder mask effects - thickness, Dk, and coverage vary by process
Fabricators account for all this using field-solver software (typically Polar Si9000) calibrated against their actual production data. That’s why their calculated widths differ from yours - and why their boards hit the target impedance.
The Solution: Specify Intent, Not Geometry
The practical workflow for controlled impedance isn’t “calculate the trace width yourself.” It’s:
- Specify your target impedance (50Ω, 100Ω differential, etc.)
- Use a recognisable trace width to flag controlled-impedance nets
- Let your fabricator calculate the actual width for their process
This is how experienced designers work, and it’s more reliable than trying to pre-calculate widths that will be changed anyway.
What to Include in Your Design Package
When you need controlled impedance, provide:
| Information | Example | Why It Matters |
|---|---|---|
| Target impedance | 50Ω ±10% | The actual requirement |
| Tolerance | ±10% (standard) or ±5% (tight) | Affects cost and process |
| Layer(s) | Layer 1 microstrip, Layer 3 stripline | Different structures = different widths |
| Differential pairs | 100Ω diff on USB, 90Ω on Ethernet | Pair identification |
| Reference plane | Ground on Layer 2 | Defines the structure |
| Trace identifier | Unique width (e.g., 6 mil for 50Ω nets) | Helps fab identify controlled nets |
Using Trace Width as a Flag
A practical technique: use a distinctive trace width for each impedance class, even if it’s not the final manufactured width. This makes controlled-impedance nets easy to identify in Gerber review.
For example:
- 6 mil width = 50Ω single-ended nets
- 5 mil width = 100Ω differential pairs
- 8 mil width = 40Ω DDR nets
Your fabricator will adjust these widths to achieve the target impedance on their process. The distinctive width just makes the nets identifiable.
Impedance Structures
Microstrip (Outer Layers)
A trace on an outer layer with a reference plane below. Part of the electromagnetic field travels through air (or solder mask), so the effective dielectric constant is lower than the bulk material.
Characteristics:
- Easier to probe and test
- More susceptible to EMI
- Solder mask affects impedance (typically -1 to -2Ω)
- Wider traces than stripline for same impedance
Stripline (Inner Layers)
A trace sandwiched between two reference planes, fully embedded in dielectric. More predictable impedance because the field is entirely within the laminate.
Characteristics:
- Better shielding from external noise
- Lower crosstalk between adjacent traces
- Tighter impedance tolerance achievable
- Narrower traces than microstrip for same impedance
Edge-Coupled Differential
Two traces routed in parallel with controlled spacing. The coupling between traces creates odd-mode and even-mode impedances; differential impedance is twice the odd-mode.
Key parameter: Spacing between traces affects coupling and differential impedance. Closer spacing = lower differential impedance.
Common Impedance Targets
| Application | Single-Ended | Differential | Typical Tolerance |
|---|---|---|---|
| General digital | 50Ω | 100Ω | ±10% |
| USB 2.0 | 45Ω | 90Ω | ±10% |
| USB 3.x | N/A | 90Ω | ±10% |
| HDMI | N/A | 100Ω | ±15% |
| PCIe | N/A | 85Ω | ±15% |
| DDR4/5 | 40Ω | 80Ω | ±10% |
| Ethernet | N/A | 100Ω | ±10% |
| LVDS | N/A | 100Ω | ±10% |
What Affects Impedance
Understanding what drives impedance helps you make good design decisions, even if you’re not calculating exact widths.
Trace Width
Wider traces = lower impedance. This is the primary variable fabricators adjust.
Dielectric Thickness
Thinner dielectric (trace closer to reference plane) = lower impedance. This is set by your stackup choice.
Dielectric Constant (Dk)
Higher Dk = lower impedance. FR-4 is typically 4.2-4.5; high-speed laminates range from 3.0-3.8.
Copper Thickness
Thicker copper = slightly lower impedance. Minor effect compared to width and height.
Differential Spacing
Closer spacing = stronger coupling = lower differential impedance. Trade-off with crosstalk and manufacturing capability.
What We Do With Your Impedance Requirements
When you order controlled-impedance boards, here’s what happens:
- Stackup proposal - We propose layer thicknesses and materials based on your requirements
- Impedance modelling - Field solver (Polar Si9000 or similar) calculates required trace widths using actual material data from the production facility
- Width adjustment - Your trace widths are modified to hit target impedance
- Test coupon - Impedance test structures added to the panel
- TDR verification - Time Domain Reflectometry confirms actual impedance after manufacturing
This is why we ask for your impedance requirements, not your calculated widths. We need to run calculations using the actual process data from the facility building your boards.
What You’ll Receive
On controlled-impedance jobs, we provide:
- Stackup drawing with actual layer thicknesses and materials
- Impedance report showing calculated values for each structure
- TDR test results from production panels (if specified)
Design Guidelines
Reference Planes
Every controlled-impedance trace needs a solid, uninterrupted reference plane. Breaks in the plane (slots, splits, via clearances) create impedance discontinuities.
Best practice: Avoid routing controlled-impedance traces over plane splits. If you must cross a split, use stitching capacitors or route on a different layer.
Via Transitions
Vias add inductance and can disrupt impedance. For high-speed signals:
- Use back-drilled or blind vias to reduce stub length
- Place ground vias near signal vias for return path
- Keep via runs short
Length Matching
For differential pairs and parallel buses, match trace lengths to control timing skew. Your fabricator doesn’t adjust for length - that’s your responsibility.
Tolerance Selection
±10% is standard and achievable with normal processes. Suitable for most digital interfaces including USB, PCIe, and Ethernet.
±5% requires tighter process control and often inner-layer routing. Costs more. Usually only needed for very high-speed serial links or RF applications.
Working with Shipco
Here’s how controlled impedance jobs flow through us:
- Send your requirements - target impedances, tolerances, layer assignments
- Factory proposes a stackup - materials and thicknesses to meet your targets, modelled using Polar Si9000 or equivalent
- Review and approval - you confirm the stackup works for your design
- Production - boards manufactured with impedance test coupons (if requested)
- Verification - TDR testing confirms compliance (if requested)
We coordinate this process and review the stackup proposals, but the impedance modelling is done by the production facility using their actual material data.
Controlled Impedance Checklist
If your design requires controlled impedance, include the following with your quote request:
Required:
- Target impedance values (e.g., 50Ω single-ended, 100Ω differential)
- Tolerance requirements (±10% standard, ±5% if needed)
- Which layers/nets require impedance control
If applicable:
- Stackup preference or constraints
- Reference plane assignments (which layer is the return path)
- Dielectric material preference (standard FR-4, high-speed, RF)
- Differential pair spacing requirements
- Thickness constraints (overall board thickness, flex areas)
- TDR test coupon and report required
We’ll handle:
- Trace width calculations using actual material data
- Stackup optimization to meet your targets
- Test coupon design and placement (if requested)
- TDR verification and reporting (if requested)
Missing something from the list? No problem - we’ll ask during technical review. But providing this information upfront speeds up the quoting process.
Frequently Asked Questions
Why does my fabricator change my trace widths?
Your calculated widths are based on nominal material properties. Fabricators recalculate using their actual process data - specific prepreg Dk values, measured etch profiles, copper foil characteristics. Their adjusted widths hit the target impedance after manufacturing; your calculated widths likely wouldn’t.
Should I use an impedance calculator?
Calculators are useful for understanding relationships (wider = lower impedance, thinner dielectric = lower impedance) and for initial stackup feasibility checks. But don’t expect calculator results to match production. For final trace widths, rely on your fabricator’s field-solver calculations.
What tolerance should I specify?
±10% for most applications. This is achievable with standard processes and is sufficient for USB, PCIe, Ethernet, DDR, and most high-speed digital. Specify ±5% only when your signal integrity analysis shows you genuinely need it - tighter tolerance costs more and may limit supplier options.
Microstrip or stripline?
Microstrip (outer layer) when you need easy probing, have EMI-tolerant signals, or want simpler stackups. Stripline (inner layer) when you need better shielding, lower crosstalk, or tighter impedance control. Many designs use both - stripline for sensitive high-speed signals, microstrip for less critical nets.
What is differential impedance?
The impedance seen by a differential signal travelling on a coupled pair of traces. It equals twice the odd-mode impedance. Common targets: 90Ω for USB, 100Ω for Ethernet and LVDS, 85Ω for PCIe.
How is impedance verified?
Time Domain Reflectometry (TDR) measures actual impedance by sending a fast-rise pulse down the trace and analysing reflections. Industry-standard equipment like the Tektronix DSA8300 series achieves sub-millimetre spatial resolution. Fabricators measure dedicated test coupons that replicate your controlled-impedance structures - same layer, trace width, stackup, and reference plane. TDR results appear in the impedance test report delivered with your boards.
Where are test coupons located?
Most commonly in panel margins - these share identical process conditions with your boards and are discarded at depaneling. Some designs use breakaway tabs that stay attached until you remove them. Physical coupons are delivered on request (for incoming QC or audit), but standard practice is fabricator retains coupons, measures them, and provides the test report.
Related Articles
- PCB Materials and Laminates Guide - Dielectric constants for different materials
- RF and Microwave Substrate Selection - Material selection for high-frequency designs
- Micro-Via Advantages in PCBs - HDI structures for high-speed routing
Need controlled-impedance PCBs? Request a quote - we calculate impedance, propose stackups, and verify results as part of our technical review.